Field
The present invention relates to integrated circuits and, more particularly, to memories that are scannable for testing.
Background
System-on-a-chip (SoC) integrated circuits (ICs) have grown increasing complex. An SoC may include a large number (e.g., 100 s) of small (e.g., 64 words by 64 bits) memories. This document uses the terms “memory” and “register file” broadly to include various forms of storage such as random access memories and multi-ported memories. The memories on an SoC are tested after fabrication to verify that they function correctly. Thorough and efficient production testing of SoC circuits has increased in complexity and importance. Prior approaches to testing these memories include built-in self-test (BIST) and ad hoc methods. Limitations of prior approaches include expense, for example, due to engineering development time, production test time, or die area used for BIST circuits.